Field of the Invention
The invention lies in the integrated technology field. More specifically, the present invention relates to an integrated circuit configuration with a substrate, which has circuit elements, and a wiring plane with interconnects, and also to a method for producing an integrated circuit configuration.
In integrated circuits, particularly in their use in smart cards and chip cards, it is possible for a potential hacker to perform an analysis of the integrated circuit, so-called “reverse engineering”, and to use the information obtained either to alter the mode of operation of the circuit or to perform a data manipulation in the memory thereof. The process can lead to undesirable consequences particularly in the case of security-relevant circuits, for instance with cash card or access authorization functions. The material covering the chip and also a part of the upper layers protecting the wiring of the chip are typically removed during the analysis. The upper interconnects that are then uncovered are usually non-security-relevant lines which can be bypassed by so-called bypass lines in order to reach farther to deeper layers and lines. With some outlay, these steps can be performed nowadays using the “FIB method” (“Focused Ion Beam”). As soon as deeper, security-relevant and thus critical lines are reached, either signals and pulses can be tapped off on the lines (so-called “probing”), or signals can be applied to these lines in order to manipulate data (so-called “forcing”).
In the past, therefore, the object has been to prevent or at least render more difficult the analysis and manipulation of the integrated circuits; on the one hand. An attempt to achieve that object has involved concealed structuring of the critical lines in the wiring plan. On the other hand, that object has been tackled by application of a dedicated, covering protective plane above the relevant wiring planes. In the case of these protective planes, called “shields”, meander-shaped or lattice-shaped lines are typically realized e.g. in pairs in the protective plane, in the event of whose interruption or short circuit for the case where different voltages are present the detecting sensor initiates an erasure of the memory, a reset or the non-functionality of other circuit sections. These lines, referred to as “passive” can likewise be embodied as unconnected, voltageless lines. In this case, they serve merely for increasing the complexity during the attack or for the purpose of confusion.
The security of the modules can be additionally increased by the passive lines described being replaced by so-called active lines in the design of the wiring plan. In the case of the active lines, signals are applied to the lines of the shield by drive circuits, which signals are analyzed by evaluation circuits and compared e.g. with reference signals owing to the possible variation of the signals, in this case the shield can only be circumvented by the very complicated laying of a bypass line by means of the FIB method.
While integrated circuits of conventional logic modules are created with an essentially manually controlled design (full-custom design), manual processing or influencing is possible only with a relatively high outlay in the case of the synthesized logic that is gaining acceptance to an ever greater extent nowadays.
In this method, functions and relationships of objects are formulated in a higher programming language, e.g. VHDL, and translated into a finished wiring plan by a compilation program. Since the protection properties of the shield lines result from functions that are independent of the actual circuit and also from their spatial position, but these cannot be fixed a priori in the synthesis method, in the case of that method it is unfortunately only afterwards that the wiring plan can be manually supplemented by protective planes, with outlay, which is in contrast to the desired efficiency and time advantage in the creation of the integrated circuit.
It is thereby precisely the integrated circuits that are created by a synthesis method that may be particularly vulnerable to hacker attack, because most of the wiring is effected in the deeper layers, while the occupancy with lines becomes less and less in the upper layers. As a result, it is possible for the potential attacker to reach the deep, security-relevant, critical lines directly e.g. from the peak measuring location using needles, without encountering lines lying in upper wiring planes.